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Integrated Circuit Test Engineering: Modern Techniques

Ian A. Grout

Chapter 4

Memory Test - all with Video Answers

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Chapter Questions

Problem 1

Consider an 8k x 8-bit single port SRAM with active low Chip Select, Read and Write signals. For the SRAM, in VHDL:
- Model the SRAM cell and verify the operation through simulation.
- Apply each of the following RAM test algorithms to the fault-free design:
- Memory Scan
- Checker Patterns
- Galloping Patterns
- March Algroithm (MATS)
- Within the model of the memory cell, model stuck-at-faults (both SA0 and SA1 faults) for the memory primary I/O
- Apply the RAM test algorithms to the faulty design and identify whether the particular algorithm will detect the fault or not
Within the above simulation exercises, store relevant simulation and analysis results in output text files for documentation purposes and further analysis.

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Problem 2

Repeat Question 1 using Verilog ${ }^3$-HDL,

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Problem 3

Repeat Question 1 except now consider a dual port SRAM.

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Problem 4

Repeat Question 3 using Verilog ${ }^{\text {² }}$-HDL.

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Problem 5

Consider an $8 \mathrm{k} \times 8$-bit ROM with a user set contents and with active low Chip Select and Read signals. For the ROM in VHDL:
- Model the ROM and verify the operation through simulation
- Within the model of the memory cell, model stuck-at-faults (both SA0 and SA1 faults) for the memory primary I/O
- Simulate to the faulty design and identify whether the particular faults are detected as would be predicted

Within the above simulation exercises, store relevant simulation and analysis results in output text files for documentation purposes and further analysis. The content of the memory address (i.e. the stored data value) should be (the value of the memory address $+5_{10}$ ).

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Problem 6

Repeat Question 6 using Verilog ${ }^*$-HDL.

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Problem 7

For the SRAM model in Question 1, consider how it may be tested as follows:
- Functional test
- Direct Access
- Scan Chain Access
- Memory Built-In Self-Test (MBIST)
- On-chip processor

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Problem 8

For commercially available discrete SRAM and DRAM ICs, identify the memory capacity and the package types that they are provided in.

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Problem 9

Identify a suitable $8 \mathrm{k} \times 8$-bit single port SRAM and using the PC based tester, repeat the experiments identified in question 1.

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Problem 10

For the SRAM in Question 9, develop a BIST structure as shown in Fig. 4.10 in order to implement a MATS algorithm. Implement the BIST using the PC based tester. Identify any specific implementation issues arising.

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Problem 11

Identify a suitable $8 \mathrm{k} \times 8$-bit ROM and using the PC based tester, repeat the experiments identified in Question 5.

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Problem 12

For the ROM in Question 11, develop a BIST structure as shown in Fig. 4.11 in order to test the complete memory. Implement the BIST using the PC based tester. Identify any specific implementation issues arising.

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