You are designing an accelerated system that performs the following function as its main task:
Assume that the accelerator has the entire $p i x$ and $f$ arrays in its internal memory during the entire computation-pix is read into the accelerator before the operations begin and $f$ is written out after all computations have been completed.
a. Show a system schedule for the host, accelerator, and bus assuming that the accelerator is inactive during all data transfers. (All data are sent to the accelerator before it starts and data are read from the accelerator after the computations are finished.)
b. Show a system schedule for the host, accelerator, and bus assuming that the accelerator has enough memory for two pix and $f$ arrays and that the host can transfer data for one set of computations while another set is being performed.