Chapter Questions
What is a sequential circuit and in what way does it differ from a combinational circuit?R input CIRCUIT CANT COPYS input CIRCUIT CANT COPYQ output CIRCUIT CANT COPY $$\overline{\mathrm{Q}} \text { output }$$ CIRCUIT CANT COPY
Explain why it is necessary to employ clocked flip-flops in sequential circuits (as opposed to unclocked flip-flops)?
What are the three basic flip-flop clocking modes and why is it necessary to provide so many clocking modes?
The behavior of an RS flip-flop is not clearly defined when $R=1$ and $S=1$. Design an $R S$ flip-flop that does not suffer from this restriction. (Note:What assumptions do you have to make?)
For the waveforms in Fig. 3.62 draw the $\mathrm{Q}$ and $\overline{\mathrm{Q}}$ outputs of an RS flip-flop constructed from two NOR gates (as in Fig. 3.2).
For the input and clock signals of Fig. 3.63, provide a timing diagram for the $\mathrm{Q}$ output of a D flip-flop. Assume that the flip-flop is(a) Level sensitive(b) positive edge triggered(c) negative-edge triggered(d) a master-slave flip-flop
What additional logic is required to convert a J K flip-flop into a D flip-flop?
Assuming that the initial state of the circuit of Fig. 3.64 is given by $C=1, D=1$, $\mathrm{P}=1$, and $\mathrm{Q}=0$, complete the table. This question should be attempted by calculating the effect of the new $C$ and $D$ on the inputs to both cross-coupled pairs of NOR gates and therefore on the outputs $P$ and $Q$. As P and $Q$ are also inputs to the NOR gates, the change in $P$ and $Q$ should be taken into account when calculating the effect of the next inputs $C$ and D. Remember that the output of a NOR is 1 if both its inputs are 0 , and is 0 otherwise$$\begin{array}{llll}\hline C & D & P & Q \\\hline 1 & 1 & 1 & 0 \\1 & 0 & & \\0 & 0 & & \\1 & 1 & \\0 & 1 & \\1 & 1 & \\0 & 1 & \\0 & 0 & \\1 & 0 & & \\\hline\end{array}$$Modify the circuit to provide a new input $S$ which, when 1 , will at any time set $P$ to 1 and $Q$ to 0 . Provide another input $R$ that will similarly set $P$ to 0 and $Q$ to 1 . Note that $R$ and $S$ cannot both be a 1 at the same time and therefore the condition $R=S=1$ need not be considered.
Demonstrate that the flip-flops in Fig. 3.65 are equivalent. Are they exactly equivalent?
Many flip-flops have unconditional preset and clear inputs. What do these inputs do and why are they needed in sequential circuits?
A T flip-flop has a single clock input and outputs $Q$ and $\bar{Q}$. Its $Q$ output toggles (changes state) each time it is clocked. The T flip-flop behaves exactly like a JK flip-flop with its J and K inputs connected permanently to a logical one. Design a T flipflop using a $D$ flip-flop.
Why haven't D and RS flip-flops been replaced by the JK flip-flop, because the JK flip-flop can, apparently, do everything a D flip-flop or an RS flip-flop can do?
What is a shift register and why is it so important in digital systems?
Design a shift register that has two inputs, a clock input and a shift input. Whenever this register receives a pulse at its shift input, it shifts its contents two places right.
Analyze the operation of the circuit of Fig. 3.66 by constructing a timing diagram (assume that $Q_0$ and $Q_1$ are initially 0). Construct the circuit using Digital Works and observe its behavior.
Analyze the operation of the circuit of Fig. 3.67 by constructing a timing diagram (assume any initial value for $Q_0$ to $\mathrm{Q}_3$ ). Construct the circuit using Digital Works and observe its behavior. This type of circuit is an important circuit in digital systems because it can be used to generate a pseudo random sequence; that is, the sequence of bits at its $\mathrm{Q}_0$ output look (to an observer) as if they constitute a random series of $1 s$ and 0 . Longer sequences of random numbers are generated by increasing the number of stages in the shift register. The input is the exclusive $O R$ of two or more outputs.CIRCUIT CANT COPY
Use Digital Works to construct the circuit of Fig. 3.68 and then investigate its behavior.
Investigate the behavior of the circuit in Fig. 3.69.
Explain the meaning of the terms asynchronous and synchronous in the context of sequential logic systems. What is the significance of these terms?
Design an asynchronous base 13 counter that counts through the natural binary sequence from $0(0000)$ to $12(1100)$ and then returns to zero on the next count.
Design a synchronous binary duodecimal (i.e. base 12) counter that counts through the natural binary sequence from $0(0000)$ to $11(1011)$ and then returns to zero on the next count. The counter is to be built from four $\mathrm{JK}$ flip-flops.
Design a synchronous modulo 9 counter using(a) JK flip-flops(b) RS flip-flops (with a master-slave clock).
Design a programmable modulo $10 /$ modulo 12 synchronous counter using JK flip-flops. The counter has a control input, TEN/TWELVE, which when high, causes the counter to count modulo 10. When low, TEN/TWELVE causes the counter to count modulo 12.
How would you determine the maximum rate at which a synchronous counter could be clocked?
The circuit in Fig. 3.70 represents a johnson counter. This is also called a twisted ring counter because feedback from the last (rightmost) stage is fed back to the first stage by crossing over the $\mathrm{Q}$ and $\overline{\mathrm{Q}}$ connections. Investigate the operation of this circuit.
Design a simple digital time of day clock that can display the time from 00:00:00 to 23:59:59. Assume that you have a clock pulse input derived from the public electricity supply of $50 \mathrm{~Hz}$ (Europe) or $60 \mathrm{~Hz}$ (USA).
Figure 3.71 gives the internal organization of a 74162 synchronous decade (i.e. modulo 10) counter.Investigate its operation. Explain the function of the various control inputs. Note that the flip-flops are master-slave JKs with asynchronous (i.e. unconditional) clear inputs.
Design a modulo 8 counter with a clock and a control input UP. When UP $=1$, the counter counts $0,1,2, \ldots$, 7. When UP $\approx 0$, the counter counts down $7,6,5, \ldots 0$. This circuit is a programmable up-/down-counter.
Design a counter using JK flip-flops to count through the following sequence.$$\begin{array}{cccc}\hline \mathrm{Q}_2 & \mathrm{Q}_1 & \mathrm{Q}_0 & \\\hline 0 & 0 & 1 & \\ 0 & 1 & 0 & \\ 0 & 1 & 1 & \\ 1 & 1 & 0 & \\1 & 1 & 1 & \\ 0 & 0 & 1 & \text { sequence repeats } \\\hline\end{array}$$
Investigate the action of the circuit in Fig. 3.72 when it is presented with the input sequence 111000001011111 , where the first bit is the rightmost bit. Assume that all flip-flops are reset to $Q=0$ before the first bit is received.figure cant copy
Design a state machine to implement the state diagram defined in Fig. 3.73.figure cant copy
Figure 3.74 provides a screen shot of a session using Digital Works. Examine the behavior of the circuit both by constructing it and by analyzing it.figure cant copy