A PC133 SDRAM supplies 64 bits ( 8 bytes) in parallel. It...

A PC133 SDRAM supplies 64 bits ( 8 bytes) in parallel. It has the following timing specifications: Clock frequency: $133 \mathrm{MHz}$ Delay for transfer of the first 8 -byte word: 7 clock cycles Delay for transfer of successive adjacent 8 -byte word: 1 clock cycle (a) If a computer without a cache fetches 64 bit words at random, what is the effective average bandwidth (in bytes/s) of the memory? (b) If a computer with a cache fetches successive 64 bit words $95 \%$ of the time, and random words $5 \%$ of the time, what is the effective average bandwidth (in bytes/s) of the memory?

A PC133 SDRAM supplies 64 bits ( 8 bytes) in parallel. It has the following timing specifications:
Clock frequency: $133 \mathrm{MHz}$
Delay for transfer of the first 8 -byte word: 7 clock cycles
Delay for transfer of successive adjacent 8 -byte word: 1 clock cycle
(a) If a computer without a cache fetches 64 bit words at random, what is the effective average bandwidth (in bytes/s) of the memory?
(b) If a computer with a cache fetches successive 64 bit words $95 \%$ of the time, and random words $5 \%$ of the time, what is the effective average bandwidth (in bytes/s) of the memory?

Key Concepts

SDRAM Timing Specifications

This concept covers the delay parameters inherent in SDRAM chips. It includes understanding that there is a fixed number of clock cycles required before the first word begins to output (the initial latency), and then a smaller delay for each successive word if they are fetched in a continuous, adjacent pattern. These timings affect the overall memory performance and are a crucial factor in calculating bandwidth.

Clock Frequency

Clock frequency is the rate at which the memory operates and is measured in MHz or GHz. It determines the duration of each clock cycle, with higher frequencies leading to shorter cycles. In performance calculations, this helps convert delays given in clock cycles into real time (seconds), which is essential for computing effective data transfer rates.

Memory Bandwidth Calculation

Memory bandwidth refers to the amount of data that can be transferred per unit time between the memory and the processor. It is determined by dividing the amount of data transferred in each operation by the total latency (initial plus any additional delay) associated with that operation. Accurate bandwidth calculation must take into account both the raw data width (such as 64 bits per word) and the timing delays.

Random vs. Sequential Memory Access

This concept distinguishes between memory access patterns. Random access involves fetching data from non-adjacent addresses, thereby incurring the full initial delay for each access. Sequential (or successive) access means that once an initial random fetch is done, subsequent accesses can take advantage of faster adjacent word transfers. This distinction significantly influences the effective performance and bandwidth of the memory system.

Cache Effects on Memory Performance

Caching affects memory performance by altering the frequency of random versus sequential memory accesses. When a cache is present and effective, most accesses are to successive memory locations (benefiting from reduced delays), while only a small percentage involve random accesses. Analyzing how these proportions impact effective average bandwidth is key to understanding overall system performance.

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