Examine the following two common mechanisms that result in degradation of transistor characteristics at very short channel lengths:
(a) Drain-induced barrier lowering (DIBL): The output characteristics in the saturation regime of drain current in a FET must become independent of the drain voltage, and only be controlled by the gate voltage. In other words, the barrier height seen at the source end of the channel for electrons must only be controlled by the gate voltage, and not the drain voltage. However, for short gate lengths a large drain voltage starts competing with the gate in controlling the barrier height at the source-injection point. Discuss typical experimental indicators of DIBL and the methods used to keep it at bay.
(b) Gate-induced drain leakage (GIDL): Band-toband tunneling currents (which are discussed in Chapter 24) are enhanced by the gate voltage in short-channel FETs on the drain side where a high field is reached. This results in gate-induced drain leakage currents. Discuss the experimental indicators and methods to counter GIDL in short-channel FETs.