In which of the following two-level circuit forms can an...

Name: Problem 41, Chapter 7: Fundamentals of Logic Design
Uploaded: 2021-09-07T16:32:59-08:00
Duration: 1 min 19 s
Channel: Ajay Singhal
Description: In which of the following two-level circuit forms can an arbitrary switching function be realized? Verify your answers. (Assume the inputs are available in both complemented and uncomplemented form.) (a) NOR-AND (b) NOR-OR (c) NOR-NAND (d) NOR-XOR (e) NAND-AND (f) NAND-OR (g) NAND-NOR (h) NAND-XOR

In which of the following two-level circuit forms can an arbitrary switching function be realized? Verify your answers. (Assume the inputs are available in both complemented and uncomplemented form.) (a) NOR-AND (b) NOR-OR (c) NOR-NAND (d) NOR-XOR (e) NAND-AND (f) NAND-OR (g) NAND-NOR (h) NAND-XOR

In which of the following two-level circuit forms can an arbitrary switching function be realized? Verify your answers. (Assume the inputs are available in both complemented and uncomplemented form.)
(a) NOR-AND
(b) NOR-OR
(c) NOR-NAND
(d) NOR-XOR
(e) NAND-AND
(f) NAND-OR
(g) NAND-NOR
(h) NAND-XOR

Key Concepts

Functional Completeness

This concept refers to a set of logic gates (or a circuit?structure) that is capable of implementing any Boolean function. In the context of two?level circuits, a particular gate configuration is functionally complete if, given access to both the uncomplemented and complemented forms of all inputs, one is able to realize every possible switching function. A key part of the analysis is checking whether the circuit form imposes any fixed “polarity” on the outputs (for example, forcing the function’s value at all–0 or all–1 input vectors), which would restrict the class of realizable functions.

Two–level Circuit Implementations

Two–level networks are structured so that the output is computed by a single gate whose inputs are generated by a layer of other gates that operate directly on the primary inputs. In standard Boolean design there are canonical forms – the Sum–of–Products (SOP) and the Product–of–Sums (POS) – which, when implemented with AND and OR gates (possibly with inverters), are universal. When the available gates are replaced by ones such as NANDs, NORs or even XORs, care must be taken because the built–in inversion or the particular algebraic properties might force the overall network to have restricted behavior.

0–Preserving and 1–Preserving Properties

A necessary condition for a circuit structure to be universal is that it does not force the output to be a fixed value for some extreme input vector (for example, always outputting 0 when all inputs are 1, or always 1 when all inputs are 0). In many of the two–level forms using NOR or NAND gates at one level combined with AND or OR gates at the next level, a ‘preservation’ property may occur – for example, f(0,…,0) or f(1,…,1) becomes fixed – making them unsuitable for implementing arbitrary Boolean functions.

Canonical Representations and Gate Equivalences

Arbitrary switching functions can be expressed in canonical forms – either a disjunction of product terms (SOP) or a conjunction of sum terms (POS). When implementing these using only specialized gates, one must account for the inherent inversion (as in NAND or NOR gates) or any specific algebraic property (as with XOR’s linear behaviour). The design challenge is to match the required canonical form with the behaviour of the available two–level circuit form. In the analysis of the given alternatives, only the arrangements that do not force fixed outputs at extreme input vectors can be universal. In this particular problem the forms that do not have inherent restrictions on f(0) and f(1) turn out to be those using a NOR gate stage feeding a NAND gate stage and vice–versa.

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