Question

Sensitize each path in the combinational part of the circuit in Figure 11.12 to obtain a complete test set that comprises as few tests as possible. Show how your test set can be applied to test this circuit. How many clock cycles are needed to perform the necessary tests?

   Sensitize each path in the combinational part of the circuit in Figure 11.12 to obtain a complete test set that comprises as few tests as possible. Show how your test set can be applied to test this circuit. How many clock cycles are needed to perform the necessary tests?
 
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Fundamentals of Digital Logic With Verilog Design
Fundamentals of Digital Logic With Verilog Design
Stephen Brown,… 1st Edition
Chapter 11, Problem 14 ↓

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12. These are the paths that do not involve any flip-flops or memory elements.  Show more…

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Sensitize each path in the combinational part of the circuit in Figure 11.12 to obtain a complete test set that comprises as few tests as possible. Show how your test set can be applied to test this circuit. How many clock cycles are needed to perform the necessary tests?
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