Question

Suppose that one of the following control signals in the single-cycle RISC-V processor has a stuck-at-0 fault, meaning that the signal is always 0 regardless of its intended value. What instructions would malfunction? Why? Use the extended version of the single-cycle processor shown in Figures 7.15 and 7.16. (a) RegWrite (b) $A L U O p_1$ (c) $A L U O p_0$ (d) Mem Write (e) $\mathrm{ImmSrc}_1$ (f) $\mathrm{ImmSr}_0$ (g) ResultSr $c_1$ (h) ResultSr $c_0$ (i) $\mathrm{PCSrC}$ (j) ALUSrc

    Suppose that one of the following control signals in the single-cycle RISC-V processor has a stuck-at-0 fault, meaning that the signal is always 0 regardless of its intended value. What instructions would malfunction? Why? Use the extended version of the single-cycle processor shown in Figures 7.15 and 7.16.
(a) RegWrite
(b) $A L U O p_1$
(c) $A L U O p_0$
(d) Mem Write
(e) $\mathrm{ImmSrc}_1$
(f) $\mathrm{ImmSr}_0$
(g) ResultSr $c_1$
(h) ResultSr $c_0$
(i) $\mathrm{PCSrC}$
(j) ALUSrc
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Digital Design and Computer Architecture: RISC-V
Digital Design and Computer Architecture: RISC-V
Sarah Harris, David… 1st Edition
Chapter 7, Problem 1 ↓

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In a single-cycle RISC-V processor, control signals dictate the behavior of the processor for each instruction. A stuck-at-0 fault in one of these signals means that the signal cannot be activated (i.e., it is always read as 0, regardless of the instruction being  Show more…

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Suppose that one of the following control signals in the single-cycle RISC-V processor has a stuck-at-0 fault, meaning that the signal is always 0 regardless of its intended value. What instructions would malfunction? Why? Use the extended version of the single-cycle processor shown in Figures 7.15 and 7.16. (a) RegWrite (b) $A L U O p_1$ (c) $A L U O p_0$ (d) Mem Write (e) $\mathrm{ImmSrc}_1$ (f) $\mathrm{ImmSr}_0$ (g) ResultSr $c_1$ (h) ResultSr $c_0$ (i) $\mathrm{PCSrC}$ (j) ALUSrc
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