Question

Write an HDL module for the FSM from Exercise 3.30. 

    Write an HDL module for the FSM from Exercise 3.30.
Digital Design and Computer Architecture: RISC-V
Digital Design and Computer Architecture: RISC-V
Sarah Harris, David… 1st Edition
Chapter 4, Problem 40 ↓

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Step 1

From Exercise 3.30, we know that the FSM has two inputs: clk (clock) and reset. The FSM also has two outputs: out1 and out2.  Show more…

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Write an HDL module for the FSM from Exercise 3.30.
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