You are examining the MAYBE hardware and nanocode to see if you can prefetch microinstructions in parallel with other computation. In the control-ROM listing you notice three things:
$\bullet$ The last phase of every microinstruction's nanocode always contains the nanoinstruction Opcode $\leftarrow \mu$ ROM; ADR + .
$\bullet$ The second-to-last phase of every microinstruction's nanocode usually contains an instruction that does not read from the microcode ROM.
$\bullet$The OP register is never loaded from anywhere except the microcode ROM.
You figure that most of the time, the OP register could be loaded simultaneously with the heretofore second-to-last nanoinstruction phase, instead of taking an additional clock cycle. You realize that for this to happen you must provide an additional path on which data can flow from the $\mu \mathrm{ROM}$ to the opcode register, simultaneously with whatever data are being transferred on the data bus during the last opcode's final phase. Before actually changing the nanocode, however, you work out the details of this new data path.
Using only eight three-state buffers and no other gates, show how to modify the MAYBE hardware to provide a dedicated data path between the microcode ROM and the $\mathrm{OP}$ register. (In the resulting machine, the $\mathrm{OP}$ register will be loadable only from the microcode ROM; it will no longer be loadable from the data bus.) The resulting circuit must still work with the old nanocode and will not yet provide any performance gain. (Note that while the OP register is never loaded from anywhere except the $\mu \mathrm{ROM}$, the $\mu \mathrm{ROM}$ is sometimes used as a source for other destinations. Thus it must still be able to drive the data bus when $\overline{\mathrm{DR} \mu \mathrm{ROM}}$ is asserted.)