EE-380 Integrated Electronic (Additional Course)
Assignment # 3
(CLO_3): (Cognitive Level C3, i.e., Analyzing)
(PLO_2: Problem Analysis)
QUESTION: A fabrication company need to design the chip having the following logic:
Y'=AB+E+CD
If you are fabricated engineer then how would u design the chip having minimum no of inter
connection using CMOS logic. Justify your answer by illustrating schematic, layout and stick
diagram of the above logic