Use nand2tetris:(assembly)Chips to implement:1-Bit Register (Bit)Register8-Register Memory (RAM8)RAM64RAM512RAM4KRAM16KCounter (PC)1. /*** 1-bit register:* If load[t] == 1 then out[t+1] = in[t]* else out does not change (out[t+1] = out[t])*/CHIP Bit { IN in, load; OUT out; PARTS: // Put your code here:} 2. /*** 16-bit register:* If load[t] == 1 then out[t+1] = in[t]* else out does not change*/CHIP Register { IN in[16], load; OUT out[16]; PARTS: // Put your code here:} 3./*** Memory of 8 registers, each 16 bit-wide. Out holds the value* stored at the memory location specified by address. If load==1, then * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward).*/CHIP RAM8 { IN in[16], load, address[3]; OUT out[16]; PARTS: // Put your code here:} 4./*** Memory of 64 registers, each 16 bit-wide. Out holds the value* stored at the memory location specified by address. If load==1, then * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward).*/CHIP RAM64 { IN in[16], load, address[6]; OUT out[16]; PARTS: // Put your code here:} 5./*** Memory of 512 registers, each 16 bit-wide. Out holds the value* stored at the memory location specified by address. If load==1, then * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward).*/CHIP RAM512 { IN in[16], load, address[9]; OUT out[16]; PARTS: // Put your code here:} 6./*** Memory of 4K registers, each 16 bit-wide. Out holds the value* stored at the memory location specified by address. If load==1, then * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward).*/CHIP RAM4K { IN in[16], load, address[12]; OUT out[16]; PARTS: // Put your code here:} 7./*** Memory of 16K registers, each 16 bit-wide. Out holds the value* stored at the memory location specified by address. If load==1, then * the in value is loaded into the memory location specified by address * (the loaded value will be emitted to out from the next time step onward).*/CHIP RAM16K { IN in[16], load, address[14]; OUT out[16]; PARTS: // Put your code here:} 8./*** A 16-bit counter with load and reset control bits.* if (reset[t] == 1) out[t+1] = 0* else if (load[t] == 1) out[t+1] = in[t]* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)* else out[t+1] = out[t]*/CHIP PC { IN in[16],load,inc,reset; OUT out[16]; PARTS: // Put your code here:}
3.5 Project
Objective Build all the chips described in the chapter. The only building blocks that you can use are primitive DFF gates, chips that you will build on top of them, and chips described in previous chapters
Resources The only tool that you need for this project is the hardware simulator supplied with the book All the chips should be implemented in the HDL language specified in appendix A.As usual, for each chip we supply a skeletal hdl program with a missing implementation part, a .tst script file that tells the hardware simulator how to test it, and a .cmp compare file. Your job is to complete the missing implementation parts of the supplied.hdl programs.
Contract When loaded into the hardware simulator, your chip design (modified .hdl program), tested on the supplied .tst file, should produce the outputs listed in the supplied .cmp file. If that is not the case, the simulator will let you know.
Tip The Data Flip-Flop (DFF gate is considered primitive and thus there is no need to build it: When the simulator encounters a DFF gate in an HDL program it automatically invokes the built-in tools/builtIn/DFF.hdl implementation.
The Directory Structure of This Project When constructing RAM chips from smaller ones, we recommend using built-in versions of the latter.Otherwise, the simulator may run very slowly or even out of (real) memory space, since large RAM chips contain tens of thousands of lower-level chips, and all these chips are kept in memory (as software objects) by the simulator. For this reason, we have placed the RAM512.hdl,RAM4K.hdl, and RAM16K.hdl programs in a separate directory.This way, the recursive descent construction of the RAM4K and RAM16K chips stops with the RAM512 chip, whereas the lower-level chips from which the latter chip is made are bound to be built-in (since the simulator does not find them in this directory).
Steps We recommend proceeding in the following order
0. The hardware simulator needed for this project is available in the tools directory of the book's software suite.
1. Read appendix A, focusing on sections A.6 and A.7.
2. Go through the hardware simulator tutorial, focusing on parts IV and V.
3. Build and simulate all the chips specified in the projects/03 directory.
