5. In this example, we will take eight instructions: load word (lw), store word (sw), add (add), subtract
(sub), AND (and), OR (or), set less than (slt), and branch on equal (beq). Compare the average time
between instructions of a single-cycle implementation, in which all instructions take one clock cycle, to a
pipelined implementation. The operation times for the major functional units in this example are 200 ps
for memory access, 200 ps for ALU operation, and 100 ps for register file read or write. In the single-
cycle model, every instruction takes exactly one clock cycle, so the clock cycle must be stretched to
accommodate the slowest instruction.
