Q3. Consider a processor having 3 level cache hierarchy. The processor has 32-bit address. Assume an exclusive cache implementation. The details of 3 level cache are as below:
L1 Cache: Direct Mapped, 4 lines, 2 words/line (1word=4bytes)
L2 Cache: 2 way set associative, 8 lines, 2 words/line (1word=4bytes), LRU replacement policy
L3 Cache: Fully associative, 16 lines, 2 words/line (1word=4bytes), LRU replacement policy
Given that the processor generates block addresses in the following order: 9,8,0,8,8,4,9,12,5,8,12,0,8,4,8
Determine the level from which each reference is serviced by filling M(for miss), H(for hit), NA(if memory reference does not reach that level) in the table below. Assume that all caches are initially empty.