Question 7
(a) Describe how the address translation is done by a linear inverted page table.
(Total: 18 marks)
(5 marks)
(b) Following part (a) above, what would be the difference in the address translation and the
advantage if a hashed inverted page table is used?
(2 marks)
(c) In a system that supports one-level, virtual memory paging, the logical address space of a
process is limited to $a$ bytes, with a total of 128K pages. The physical address is byte
addressable, which contains 2M bytes.
Use the following values for $a$ based on the 7th digit of your student ID.
7th digit of your student ID
Odd
Even
Values for $a$
$a = 8M$
$a = 32M$
(i) What is the size of a page (in bytes) in the system?
(1 mark)
(ii) How long is the page offset field in the logical address?
(1 mark)
(iii) How long is the page number field in the logical address?
(1 mark)
(iv) How long is the length of the physical address?
(1 mark)
(v) How many page table entries are there in the page table of the system?
(1 mark)
(vi) Assume each page table entry occupies 2 bytes, which stores the frame number and $n$
control bits. Determine the value of $n$. Then, find the total size of the page table (in
bytes). Show your calculation steps.
(3 marks)
(d) For the computer system in part (c), assume the linear inverted page table is used instead.
Calculate the size of the inverted page table (in bytes) if the system supports 16384 processes
and each inverted page table entry contains the process ID in binary, the page number portion
of a logical address, and one control bit: the valid/invalid bit. Show your calculation steps.
(3 marks)
