The circuit below has two identical flip-flops which are clocked at 25MHz, and the
synchronising flip-flop is sampling an asynchronous 5MHz (data rate) input.
Given that Ï„=0.31ns, To =9.6 x 10 -18 s and t su =1ns for a D-type flip flop from a
typical 0.25μm CMOS ASIC process.
• Calculate the resolution time and MTBF of the circuit.
• If the clock frequency in the circuit above is quadrupled, calculate the effect
on MTBF and comment on its change?
• Show how the circuit above can be modified to improve the MTBF, by adding
an additional flip-flop. Give an expression to estimate the new MTBF, and
calculate the new value.
D Q D QCombinational
logic
CLOCK
6.7 ns
Synchroniser Flip-flop in
design
Asynchronous
input