Consider the following 32-bit MIPS multi-cycle datapath design for lw, sw, beq, j and R-type (add, sub, and, or, srl) instructions. The system operates at a clock frequency of 0.2 GHz.
Assume that sw $1, 20 ($2) instruction is executed on this datapath. The contents of PC when sw is being executed is (20)8. What will be the contents of target register at the end of 2<sup>nd</sup> clock cycle?