2. The mouse controller in a MIPS-based computer has three 8-bit registers labeled mouse_status, mouse X, and mouse_Y. The mouse_status register indicates the mouse status as follows:
bit 0 (LSB): 1 means LeftClick; 0 means no LeftClick
bit 1: 1 means MiddleButtonClick; 0 means no MiddleButtonClick
bit 2: 1 means RightClick; 0 means no Right Click
bit 7 (MSB): Change in Mouse Position
mouse X and mouse_Y registers indicate the X-xoordinate and Y-coordinate (respectively) of the mouse's current position.
When the mouse is moved on its pad, its controller enters the new X-coordinate and Y-coordinate values into mouse X and mouse Y, sets the MSB of mouse_status to 1, and sends an interrupt. When an end user clicks one of the mouse buttons, the mouse controller sets the appropriate bit in mouse status to 1, and sends an interrupt.
Upon receiving the interrupt, the system switches to Kernel Mode, and transfers control to the interrupt entry point in the OS' System Call Layer. From there, control eventually goes to the Mouse ISR (interrupt service routine).
Write a MIPS assembly-level ISR to process the interrupt. The ISR returns the X-coordinate, Y-coordinate, LeftClick, MiddleClick, and RightClick values through registers $v0, $v1, $a0, $a1, and $a2. It returns control to where it was called from. It does not concern itself with enabling and disabling interrupts.
