1. If the following code segment is pipelined, which
are the instructions affected by data hazards and which
are not? Justify your answer with appropriate
explanations and pipeline block diagram.
ADD R1,R2,R3
MUL R2, R4,R5
AND R6,R2,R7
OR R8, R6, R4
XOR R9, R8,R3
6 marks
2. What is associative mapping in cache? Prove that set
associative mapping have both the properties of direct
mapping and associative mapping
4 marks
3. Explain with examples how the delayed branch
scheme reduces branch penalty
3 marks
2 marks
4. Write short note on Flash memory used in SSDs
Note:
1. Refer the handout for basic information and use
the Internet for detailed information of the topics
2. Solve it individually, any attempt to share the
solution will result in zero marks for both parties
3. Solution will be checked for plagiarism(if >25%,
there will be penalty)
