DGTL 106 Digital 1 Theory
Assignment 4
Questions:
Instructor: Anthony Voykin
1. What is the frequency of the most significant bit from a MOD-12 counter that is
clocked at a frequency of 10kHz.
2. An asynchronous counter is designed using 74LS76A devices and configured as a
MOD-14 up counter. What is the worst case propagation delay from the active
edge of the clock input to the change in the most significant bit?
3. Design a circuit that will work as a 2-bit synchronous down counter. Sketch the
timing diagram showing the clock, $Q_0$ and $Q_1$.
4. Design a 2-bit synchronous count with an extra input called UP/DOWN, which
will be used to control the count direction. For example, when the input is high,
the counter will count up and when the input is low the counter will count down.
Sketch the timing diagram showing the clock, $Q_0$, $Q_1$ and UP/DOWN.
5. Design a synchronous counter circuit using D flip flops to emulate the state
transition diagram provided. Add an active low input called RST that will
asynchronously force the output to 101 when asserted. Show all of your design
work. Include a Multisim schematic and timing diagram proving your design
works.
