Obtain a minimal state table for a synchronous sequential circuit of Moore-type with an
input signal (w), and an output signal (z). The input sequence will generate the output 1 if it
detects either input sequence 110 or 101, also overlapping sequences are valid (eg. 1101, is
110 followed by 101, will give output 00011).
a) Draw the state diagram.
b) Without writing VHDL code, explain how you can use one-hot code to force the synthesis
tool to encode the states.