4a. if you have a 4 stage instruction [fetch/decode, execute, memory, write back], and each of these
stages takes 1.5 clock cycles, how long would this take for 3 instructions on a non-pipelined computer?
4b. Then pipeline these 4 stages in each of your instruction [each stage = 1.5 clock cycles), where you
fetch/decode the next instruction as soon as the previous fetch/decode is done. hHw long does this
take?
-FIBS-
1. What are three basic steps for Tomasulo's algorithm?
2. Choose your favorite data hazard, explain it, and give a good example
3. If you have no pipeline stalls, what is the pipeline speedup for a depth of 3 pipelines?
4. what is one reason that pipelining is hard to implement, and explain with an example