6.6 Design a four-bit shift register with parallel load using D flip-flops. There are two control
inputs: shift and load. When shift =1, the content of the register is shifted by one posi-
tion. New data are transferred into the register when load =1 and shift =0. If both
control inputs are equal to 0 , the content of the register does not change. (HDL-see
Problem 6.35(c), (d).)