1. LOAD R, #1
2. LOAD S, #1
3. LOAD T, #(k-2)
4. ADD AC, R, S
5. T--
6. LOAD R, S
7. LOAD S, AC
8. BRP 4, T
// SUB T, T, 1
9. STOR M, AC
(a) Explain the effect of (conditional) branch instructions on the pipeline and de-
scribe the delayed branch technique.
(6 marks)
(b) Show the pipeline activity when the code is executed with input value k=4 on
a RISC computer using the delayed branch technique. There are five pipeline
stages: fetch, decode, register read, execute and write back, and there is an
instruction cache on board (initially empty) that can store ten decoded instruc-
tions. You can assume that certain instructions skip some of the stages, but
make these assumptions explicit.
(14 marks)
