1. LDUR X0, [X11, #0]
2. LDUR X1, [X10, #4]
3. ADD X3, X0, X1
4. SUB X3, X0, X0
5. ADD X4, X3, X12
1. List the true data dependencies (Read-after-write) in the above code. Use the number
next to the instruction to identify instructions. For example, If the Instruction with line
number x has a dependency on instruction with line number y. Then state that
"Instruction x on instruction y".
Note: List all dependencies, respective of whether they cause stalls in the pipeline or
not.
2. Assume 5-stage pipeline with no forwarding, and each stage takes 1 cycle.
a. Show the pipeline diagram for the instruction sequence.
b. Assuming that the processor stalls on a hazard. How many times does the processor
stall? How long is each stall (in cycles)? What is the execution time (in cycles) for
the whole program?
c. Assume the 5-stage pipeline with full forwarding. Show the pipeline diagram with
stalls if needed. What is the execution time (in cycles) for the whole program?