5 - In this question, you will implement and simulate a simple receiver.
a) First, using MATLAB, generate a number of random 11-bit data. Then design a transmitter that, upon receiving each of these 11-bit data, adds appropriate parity bits and finally sends them in the form of 15-bit data. Finally, you should store these 15-bit data in a file. Also, store the initial 11-bit data in a file for later validation purposes.
b) Write a Verilog code that receives 15-bit data as input and, based on the parity bits, if the data reception process is correct, it places the 11-bit data on its output and sets the valid signal to high for one clock cycle. Otherwise, it discards the 15-bit data and increments the error output by one.
c) Now, write a testbench that reads the 15-bit inputs from the file saved in Part A and applies them to the structure in Part B. Write the output of the Part B module to a file. Then, in MATLAB or the testbench, compare the output of your module with the initial 11-bit data and verify the functionality of your circuit.
d) For a more comprehensive validation, introduce noise to the file containing the input data and examine the changes in the error signal.