Question 2. Given: You have been hired to layout the design for a Ripple Carry Adder (RCA) for an add R-type instruction in a CPU with a 32-bit wide ALU. You shall use a one-bit Full Adder constructed using five 2- input Boolean gates, plus any other gates needed. Part 2.1. How many Boolean gates are required for this RCA? a) 5 gates (2 XOR, 2 AND, 1 OR) b) 10 gates (4 XOR, 4 AND, 2 OR) c) 50 gates (20 XOR, 20 AND, 10 OR) d) 160 gates (64 XOR, 64 AND, 32 OR) e) 320 gates (128 XOR, 128 AND, 64 OR) Part 2.2. If the propagation delay of each Boolean gate is 50 psec, then in the worst case how long would addition of two 32-bit numbers require using this RCA? a) 50 psec b) 1600 psec c) 4.8 nsec d) 480 nsec e) 1600 nsec Part 2.3. Suppose the clock period of this CPU is 1.2 nsec. What would the CPI for add be? Here assume any operations associated with an add instruction besides the RCA itself require negligible time (zero time for fetching instructions and operands from memory, zero time to access registers, zero time for control signals, etc.). a) 1.0 b) 1.7 c) 2.0 d) 3.0 e) 4.0