Problem 3 (20 points)
Assume that this CMOS fabrication process allows a variation of the $V_{T0,n}$ value by ±5% around its
nominal value, and a variation of the $V_{T0,p}$ value by ±12% around its nominal value. If all other
parameters are fixed (W, L, ?, Cox), calculate the upper and lower limits of the switching threshold of
interest?