I. Design and simulate a Full Adder circuit using minimal NAND gates for the carry out and \overline{XOR} gates for the sum (be sure to show development of both equations in your report). Use A, B, Cin for the inputs, S and Co for the outputs and use the file name ADDsss. Under file select 'Create Symbol Files for Current File.' Then simulate it again using the default symbol. Be sure to show (a) truth table, (b) Karnaugh maps, (c) Boolean algebra, (d) final equations used in your solution, and (e) the symbol for ADDsss (find in the directory as ADDsss.bsf). These details may vary slightly based on what version of Quartus II you are using.