Consider the following ARMv8 code below.
ADD X3, X3, 0x1
LSL X4, X4, 0x3
ADD X4, X3, X4
LDUR X4, [X5, 0x0]
ADD X12, X4, 0x1
LSL X9, X12, 0x3
ADD X9, X13, X9
LDUR X10, [X9, 0x0]
ADD X7, X7, X10
STUR X7, [X4, 0x0]
SUB X0, X5, X7
Select ALL statements that are true. Assume that Writeback and Decode can occur on the same
clock cycle.
None of these statements are true.
With no forwarding, there are 14 stalls.
With no forwarding, there are 4 stalls due to load-use hazards.
There are 9 data hazards in this code.
With perfect forwarding as seen in class, the CPI of this code is 1.