A set-associative cache with the following parameters:
-Line size: 1024 bytes
-Number of lines: 8
-Number of ways: 4
-Address lines: 16-bit starts from the state where all lines are invalid (e.g. empty cache).
Suppose the CPU sends the following sequence of memory byte addresses to the cache: 5388, 12900, 10744, 6438, 13459, 9812, 9962, 12772, 10872, 15619, 15363, and 3095.
Complete the fields below and for every request/address, specify:
1) the Block ID of the address,
2) the Set ID that the address is mapped to in the cache, and
3) if the request is hit or miss.