Q1. Pipeline Basics and Speed-up
We begin with a computer implemented in single cycle unpipelined implementation. When the stages
are split by functionality, the stages do not require exactly the same amount of time. The original
machine had a clock cycle time of 7 ns. After the stages were split, the measured times were IF, 1 ns;
ID, 1.5 ns; EX, 1 ns; MEM, 2 ns; and WB, 1.5 ns.
(a) If we build a 5-stage pipelined machine, what should be the clock cycle time of the 5-stage
pipelined machine? Assume the same measured times above for the stages and use 0.1 ns for the
pipeline register delay.
(b) If there is a single-cycle stall every 4 instructions for the pipelined implementation, what is the
CPI of the new machine?
(c) What is the speedup of the pipelined machine above (with the stall assumption) over the single-
cycle machine?
(d) If we build a multi-cycle unpipelined machine and execute a program that consists of 10% load,
10% store, 60% ALU, 20% branch instructions. What is speedup of the pipelined implementation
with the single cycle stall in (b), compared to the multi-cycle implementation? Note that multi-
cycle unpipelined machine uses only the stages needed for processing each instruction.
