Problem 1: Complementary CMOS:
a. Implement the equation (with the minimal number of transistors) X =
((A + B)(C + D + E) + F)G using complementary CMOS ). Points: 30
b. The speed of the circuit also depends on input patterns. For example, a two-input NAND
gate will have different speeds for inputs 00, 01, 10 and 11. Which input pattern(s) would
give the worst and best equivalent pull-up or pull- down resistance? Assume that the
resistance of all transistors (both pMOS and nMOS) is 10 ohm. Points: 40
c. Calculate equivalent resistance of the pull-down network when input vector
ABCDEFG=1111111. Points: 30.