Simulate this design with the aid of a 'graphical testbench' (also known as a "Test Bench Waveform" file), using the Xilinx ISE v10.1.03 software.
I need new code and correct with different variables, which have not been available before on your website.
Assignment 1
Design in VHDL a 4-bit universal decimal counter as presented below:
D1 D0
10 QO
J/D
LD Synchronous Parallel Load D3,..,.D0 Parallel Data Inputs Q3,.-.Q0 Data Outputs RST Asynchronous Reset Input U/D Count direction (up/down)
RST
As described by the following function table:
Asynchronous Reset Count Down Count Up Synchronous Parallel Load
Simulate this design with the aid of a graphical testbench (also known as a Test Bench Waveform file), using the Xilinx ISE v10.1.03 software. You must set the color scheme of your simulation waveforms to the Classic color scheme, via the Edit Preferences.. ISE Simulator (ISim) Simulation Waveform Colors menu.
Correct type of testbench, using the required color scheme.
Version and th
What you should submit
You should submit a formal report explaining your design and your results
Specifically, your report should contain at least the following information: a) An introduction including the design brief, b) A background section on counters, their types and their operation, c) A section explaining how you've solved the design task given to you and if applicable why you've selected a particular solution out of several possible, d) The complete listing of the code you've written, bearing in mind good programming and design practice, e) A legible screenshot of your graphical testbench (or testbenches if using more than one), f) The results of the simulations carried out (i.e. suitable, legible and detailed simulation waveforms) accompanied by detailed comments and explanations, and g) Conclusions (and possible further improvements if applicable).
