[SNOOPY CACHE COHERENCE] We studied the invalidation-based write- back cache coherence protocol based on three states: Invalid (I) where the block is considered invalid, Shared (S) where the block may exist in more than one cache (and is consistent with main memory) and Exclusive (E) where the block exists in exactly one cache and the block is not consistent with main memory.
Assume that blocks A1 and A2 map to the same cache block but A1 != A2. Using the invalidation-based write-back cache coherence protocol for three processors and eight sequential events.
For each event, show the states, state transitions, and bus transactions when using the protocol. Write the following: Processor Action (given), State in P1, State in P2, State in P3, State in P4, Bus Action and Data Supplied By.
(1) processor 1 reads a shared variable A1.
(2) processor 3 reads A1,
(3) processor 3 writes a new value into its cached variable A1.
(4) processor 1 reads into its cached value of A1, (5) processor 3 reads A2.
(6) processor 2 reads A1,
(7) processor 1 reads A2, and
(8) processor 3 writes A2.
Processor
Action
Read Miss in P1 for A1
State in State in State in Bus Action
P1
P2
P3
Data
Supplied By
