A MOSFET layout is illustrated in the diagram. Given: For substrate, NA = 10^15 cm^-3 and Np = 5x10^18 cm^-3 for the source and drain wells. The bias voltages are: Vsp = 1V, VGB = 3V, and Vps = 4V. Assume V = 1V.
a) If the lateral diffusion under the gate is 0.2 um and the oxide thickness is tor = 30 nm, what is the total gate capacitance, Cor?
b) What is the MOSFET transconductance, gm, under the given bias?
c) Explain the source of the three types of capacitance in MOSFETs.
d) If Cdep = 5 x 10^-11 F/cm and Cdep = 1 x 10^-9 F/cm^2, calculate the total source and drain depletion capacitances. Assume the grading coefficient to be 0.5.
e) Based on the lateral diffusion value of part a) and assuming CGB,ovt = 1 x 10^-12 F/cm, estimate the three extrinsic MOSFET capacitances.
f) The intrinsic capacitances, Ces and Ceo, change with biasing condition. What are their values under the given bias conditions?
g) Draw the high-frequency, small-signal representation of this MOSFET device at the given DC bias. Ignore ro.