Q2)
[2+(2+2)+(2+2) marks]
In the circuit below, QA is the MSB, QD is the LSB. CLR is active high. The combinational
elements have some non-zero delay. Find
Clock
$S_1$
1
4 bit counter
3
QA 4
QB 5
CLR
QC 6
QD 8
2
a) Find the CLR signal as a function of QA, QB, QC, QD. [2 marks]
b) Write down the counting cycle in decimal for the above circuit
i. Assuming CLR is synchronous [2 marks]
ii. Assuming CLR is asynchronous [2 marks]
c) What should be CLR as a function of QA, QB, QC, QD. To get the counting cycle as
(0-1-2-3-4-5-6-7-0-1-2-3-4-...)
i. Assuming CLR is synchronous [2 marks]
ii. Assuming CLR is asynchronous [2 marks]