Texts: I want to ask this computer organization question. Please give me solutions in detail and teach me how to solve it. Thank you.
3. a) Consider a hypothetical machine with 512 words of cache memory. They are in a four-way set associative organization, with a cache block size of 64 words, using LRU replacement algorithm. Suppose the cache hit time is 10ns. Suppose the machine can access 4 words of memory in parallel, and the time to transfer the first 4 words from main memory to cache is 60ns, while each subsequent 4 words require 1ns. Consider the following read pattern (in blocks of 64 words, and block id starts from 0): 0125325311790607987911122451215121315. Assume each block contains an average of 24 memory references.
i) What is the cache miss penalty, i.e., time to transfer one block of data from main memory to cache memory? [2]
ii) Write down the content of the cache memory (for all the blocks) at the end of the memory references, assuming that the cache is empty at the beginning. [5]
iii) Write down the number of cache misses (the first reading of a block is also considered a miss) and the cache hit rate. [3]
iv) Calculate the average memory access time. [2]
b) Virtual Memory and Cache Memory are based on the same principle. However, their actual implementations are quite different.
i) Explain why Virtual Memory uses table-lookup for address translation but not in cache memory. [3]
ii) Explain why Write-through strategy can never be used in Virtual Memory. [2]
c) Consider a Hard Disk with an average seek time of 12ms, 1ms for moving to adjacent track, and rotation speed of 5400rpm, with an average of 400 sectors/track, and each sector is 512 bytes.
i) What is the average rotation latency? [2]
ii) What is the time required for reading 1 sector to rotate under the read/write head? [2]
iii) What is the time to read 5 sectors, located in 5 different random tracks? [2]
iv) What is the time to read consecutive 5 sectors, located in the same track? [2]
v) Explain why HDD defragmentation can improve system performance. [2]
