4. Using the following Shift register with load-reducing NOT gates and any number of AND and
OR gates, design the following circuits; do not forget the CLOCK. (2.5 Points)
(a) A Moore-model circuit that outputs 1 if the last four input have been twice repeated alternating
Os and 1s, e.g., 0011, 1001,..., 0110. (+1.0)
S
$q_1$
S
$q_2$
S
$q_3$
S
$q_4$
R
$q_1'$
R
$q_2'$
R
$q_3'$
R
$q_4'$
Clock