II. Given the Block Diagram:
X
F
Y
Z
And Requirements:
3 Inputs labeled as X, Y, Z with X the MSB
Active Low Output labeled as Fsss
Operation: The output will be active when both X and Y are '0' or Y and Z are both '1.'
The output will be '1' for all other cases.
A. Create the truth table and develop the canonical SOP equation using the above
specifications. Then implement your equation using schematic capture and simulate.
B. Simplify your equation from (A) using Boolean algebra (showing the theorems
you used) and check your algebra using a Karnaugh Map. Simulate your new
equation using schematic capture.
C. Using your simplified equation from (B), create a VHDL file and simulate, but
change the output variable to Gttt, where ttt are the last three digits of another
partner's SID. To get full credit for your vhdl file, be sure to include Comments as
included on previous page.