For the following circuits, assume Tsetup and Thold are \( 0.1 \mathrm{~ns}, \mathrm{Clk}->\mathrm{Q} \) is 1.0 ns , all gate delays are 1.0 ns , and the clock period is 100 ns . "In" is an external input to the circuit, and all DFFs were initialized to 0 before the circuit started running. For each circuit, figure out whether OUT can ever be a 1. If it can, give a specific scenario when this can happen. If it cannot, explain why.
"In" is asynchronous in relation to the clock
A.)
B.)
C.)
D.)