A binary decoder with $n$ input variables provides $2^n$ outputs, each of which is associated with a unique combination of input bits. Since any Boolean function can be expressed in sum-of-product form, a binary decoder, together with an external OR gate, provides a hardware implementation of the function. Therefore, any combinational circuit with $n$ inputs and $m$ outputs can be implemented with an $n$-to-$2^n$ binary decoder and $m$ OR gates. Let us take a following combinational logic as an example:
$o = x'y + xy'z'$
We have the following truth table for the logic:
$x$ $y$ $z$ $o$
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
and the logic can be rewritten as follows:
$o = x'y + xy'z' = x'yz' + x'yz + xy'z'$
Based on this, we can implement the logic with a 3-to-8 binary decoder and an OR gate as follows:
Now, design a 1-bit full adder which has three 1-bit inputs and two 1-bit outputs, using the same method. (Only use a binary decoder and OR gates.)
