I need help solving my VHDL error. I can't figure out what I am doing wrong.
Files Added: Adders - Adder_8bit.vhd
-- Lab2 - Adder_8bit Created by -- March 30, 2024
```vhdl
library IEEE;
use ieee.std_logic_1164.all;
use work.Adders.all;
ENTITY Adder_8bit IS
PORT (
A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Cin : IN STD_LOGIC;
Cout : OUT STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END Adder_8bit;
ARCHITECTURE STRUCTURE OF Adder_8bit IS
SIGNAL C : STD_LOGIC;
BEGIN
Adder4bit1 : Adder_4bit PORT MAP (A(3 DOWNTO 0), B(3 DOWNTO 0), Cin, C, SUM(3 DOWNTO 0));
Adder4bit2 : Adder_4bit PORT MAP (A(7 DOWNTO 4), B(7 DOWNTO 4), C, Cout, SUM(7 DOWNTO 4));
END STRUCTURE;
```
Error (10381): VHDL Type Mismatch error at Adder_8bit.vhd(23): indexed name returns a value whose type does not match "std_logic", the type of the target expression
Error (10476): VHDL error at Adder_8bit
Error (10476): VHDL error at Adder_8bit
Error (10558): VHDL error at Adder_8bit
Error: Quartus II Analysis & Synthesis successful. 4 errors, 0 warnings
Error: Quartus II Full Compilation was unsuccessful. 6 errors, 0 warnings
