LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HA IS
PORT (x, y: IN STD_LOGIC;
sum, cout: OUT STD_LOGIC);
END;
ARCHITECTURE HA_arch OF HA IS
BEGIN
sum <= x XOR y;
cout <= x AND y;
END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FA IS
PORT (x, y, cin: IN STD_LOGIC;
sum, cout: OUT STD_LOGIC);
END;
ARCHITECTURE FA_arch OF FA IS
COMPONENT HA
PORT (x, y: IN STD_LOGIC;
sum, cout: OUT STD_LOGIC);
END COMPONENT;
SIGNAL sum1, cout1, cout2: STD_LOGIC;
BEGIN
HA1: HA PORT MAP (x, y, sum1, cout1);
HA2: HA PORT MAP (cin, sum1, sum, cout2);
cout <= cout1 OR cout2;
END;
