1) Using Synthesizable Verilog behavioral modeling, describe an n-bit circuit (i.e. parameterizable)
that has four n-bit unsigned inputs A, B, C, and D, and two control inputs S1, and So. The circuit
produces an 2n+1-bit output Y according to the following table: (No delays)
S1 So Function
0 0 Y ? AVERAGE (A,B,C,D), i.e. Y equals the (integer) average of the 4 inputs
0 1 Y ? MAX (|A ? B|, |C ? D|), i.e. Y equals the maximum of the absolute
differences between A & B, and C & D.
1 0 Y ? MIN (|A ? B|, |C ? D|), i.e. Y equals the minimum of the absolute
differences between A & B, and C & D.
1 1 Y ? (A ? B)² + (C ? D)², i.e. Y equals the sum of the squares of the differences
between A & B, and C & D.
Assume that the * and + operators are synthesizable, but not the ?, **, and the / operators.
2) Write a test bench and simulate your circuit with the following input values (set n=4). Print the
simulation results and comment on the results of each test value:
All Values below are in decimal
? Set A=8, B=12, C=10, D=5, Then S1, So=(0,0), (0,1), (1,0), and (1,1)
? Set A=5, B=12, C=13, D=7, Then S1, So=(0,0), (0,1), (1,0), and (1,1)
