3. Consider the following circuit
D
Inverter timing:
Propagation delay $t_p = 20 \text{ pS}$
CLK
Flip-Flop timing:
Setup time $t_{su} = 30 \text{ pS}$
Hold time $t_{hold} = 10 \text{ ps}$
Clock-to-Q delay $t_{clk-Q} = 50 \text{ pS}$
Assume the CLK signal has a square waveform with 50% duty cycle.
a. Draw the waveforms of signals CLK, D, and Q for 4 clock cycles.
b. What is the ratio between the oscillation frequency of the signals CLK and Q?
c. For this circuit to operate correctly, determine the maximum CLK frequency based on the
given timing characteristics of the flip-flop and the inverter.
d. Would a hold time violation occur on the flip-flop at any CLK frequency? Why or why
not?
e. If this circuit dissipates 100 Micro-Watts when operating at $V_{dd} = 2.5 \text{ Volts}$ and CLK
frequency of 1 GHz, estimate the power dissipation of the circuit when operating at
$V_{dd} = 1.25 \text{ V}$ and CLK frequency of 100 MHz. Assume the power dissipation is dominated
by the switching (dynamic) power. ($1 \text{ GHz} = 10^9 \text{ Hz}$ and $1 \text{ MHz} = 10^6 \text{ Hz}$)
