2.
a. (5 points) Write a SystemVerilog module named minority. It receives three one-bit inputs, a, b,
and c. It produces one one-bit output y that is TRUE if at least two of the inputs are FALSE.
module minority (input logic a, b, c,
\quad output logic y),
assign y = (~a and ~b) | (~a and ~c) | (~b and ~c);
endmodule
b. (5 points) Write a self-checking testbench for this module. You don't need to use a test vector
file. Test every possible value of the inputs.
module testbene
