2. In the schematic below,
(i) Estimate the Minimum register-register delay
(ii) Is there a hold-time violation if the Tc2q delay is halved?
(iii) Assuming a Tc2q of 2ns, if the cycle time is 20ns, and the Setup Time increased to 5ns is there a
setup time violation?
UFF1
D Q
UOR4
2/3
Min path
CK
UBUF2
UNAND6
2/3
UFF3
Q
3/4
UNANDO
1/2
CK
UFF2
D Q
3/4
DFFS:
UOR2
Max path
Tsu = 3ns
Thd = 4ns
Tc2q = 5ns
CK
2/3 = \"Min/Max Delay\"