2 Scoreboard
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Dynamic scheduling can be implemented with different architectures as Scoreboard or the Tomasulo
organisation.
a) Explain the advantages of dynamic instruction scheduling at run-time in hardware; mention its
possible disadvantages.
b) What are the hardware-innovations of the Tomasulo architecture?
c) There are several types of data-hazards (RAW, WAR, etc.). Assuming an out-of-order proces-
sor, explain the data-hazards in listing.
; Multiplication
MUL.D F0, F2, F4
ADD.D F6, F0, F4 ; Addition
L.D F0, 10 (R2) ; Load
DIV.D F4, F2, F0 ; Division
SUB.D F4, F6, F8 ; Subtraction
Listing 1: Sample assembler code
d) Compare the behavioural of Scoreboard and Tomasulo organisation with respect to WAW and
WAR hazards.
e) Consider a scoreboard architecture with an integer unit, a load/store unit and the following float-
ing point units: one adder/subtractor, one divider, and two multipliers. The machine executes
the assembler code of listing 1. Determine in which clock cycle each instruction is issued, com-
pletely executed, and finished (i.e., result written). Assume that addition/substraction takes 2
cycles, load/store takes 1 cycle, multiplication takes 6 cycles and division takes 9 cycles.
Hint: You only have to fill the Instruction Status table. You can, but you do not have to, use the
functional unit status and register result status tables (as many as needed) to track the status
of the instructions.
Instruction status
Instruction Dst Srcj Src k Issue Read Exec Write
Oper. Comp Res.