Assume that you have a system that contains a 16-word cache (C=16). Consider the following RISC-V assembly code:
addi t0, zero, 4
addi s0, zero, 0
loop: beq t0, zero, done
lw t1, 0x30(s1)
lw t2, 0x74(s1)
lw t3, 0x54(s1)
lw t3, 0x50(s1)
addi t0, t0, -1
j loop
done:
Part 2: Two-way Set Associative Cache, b = 1 word
1) Fill in the correct size for the cache fields (Memory Address size is 32-bit):
Tag Set Byte Offset